/**
 * 8080a emulator
 * triton & ic
 *
 * based on libz80, Marat z80 , SIEmu & others z80 cores floating the web
 */

#ifndef __OPCODES_H__
#define __OPCODES_H__

enum EEopcodes
{
  NOP, LD_BC_i, LD_mBC_A, INC_BC, INC_B, DEC_B, LD_B_i, RLCA,
  EX_AF_AF, ADD_HL_BC, LD_A_mBC, DEC_BC, INC_C, DEC_C, LD_C_i, RRCA,
  DJ_NZ, LD_DE_i, LD_mDE_A, INC_DE, INC_D, DEC_D, LD_D_i, RLA,
  JR, ADD_HL_DE, LD_A_mDE, DEC_DE, INC_E, DEC_E, LD_E_i, RRA,
  JR_NZ, LD_HL_i, LD_mi_HL, INC_HL, INC_H, DEC_H, LD_H_i, DAA,
  JR_Z, ADD_HL_HL, LD_HL_mi, DEC_HL, INC_L, DEC_L, LD_L_i, CPL,
  JR_NC, LD_SP_i, LD_mi_A, INC_SP, INC_mHL, DEC_mHL, LD_mHL_i, SCF,
  JR_C, ADD_HL_SP, LD_A_mi, DEC_SP, INC_A, DEC_A, LD_A_i, CCF,
  LD_B_B, LD_B_C, LD_B_D, LD_B_E, LD_B_H, LD_B_L, LD_B_mHL, LD_B_A,
  LD_C_B, LD_C_C, LD_C_D, LD_C_E, LD_C_H, LD_C_L, LD_C_mHL, LD_C_A,
  LD_D_B, LD_D_C, LD_D_D, LD_D_E, LD_D_H, LD_D_L, LD_D_mHL, LD_D_A,
  LD_E_B, LD_E_C, LD_E_D, LD_E_E, LD_E_H, LD_E_L, LD_E_mHL, LD_E_A,
  LD_H_B, LD_H_C, LD_H_D, LD_H_E, LD_H_H, LD_H_L, LD_H_mHL, LD_H_A,
  LD_L_B, LD_L_C, LD_L_D, LD_L_E, LD_L_H, LD_L_L, LD_L_mHL, LD_L_A,
  LD_mHL_B, LD_mHL_C, LD_mHL_D, LD_mHL_E, LD_mHL_H, LD_mHL_L, HALT, LD_mHL_A,
  LD_A_B, LD_A_C, LD_A_D, LD_A_E, LD_A_H, LD_A_L, LD_A_mHL, LD_A_A,
  ADD_B, ADD_C, ADD_D, ADD_E, ADD_H, ADD_L, ADD_mHL, ADD_A,
  ADC_B, ADC_C, ADC_D, ADC_E, ADC_H, ADC_L, ADC_mHL, ADC_A,
  SUB_B, SUB_C, SUB_D, SUB_E, SUB_H, SUB_L, SUB_mHL, SUB_A,
  SBC_B, SBC_C, SBC_D, SBC_E, SBC_H, SBC_L, SBC_mHL, SBC_A,
  AND_B, AND_C, AND_D, AND_E, AND_H, AND_L, AND_mHL, AND_A,
  XOR_B, XOR_C, XOR_D, XOR_E, XOR_H, XOR_L, XOR_mHL, XOR_A,
  OR_B, OR_C, OR_D, OR_E, OR_H, OR_L, OR_mHL, OR_A,
  CP_B, CP_C, CP_D, CP_E, CP_H, CP_L, CP_mHL, CP_A,
  RET_NZ, POP_BC,   JP_NZ, JP,       CALL_NZ, PUSH_BC, ADD_i, RST_0H,
  RET_Z,  RET,      JP_Z,  PFX_CB,   CALL_Z,  CALL,    ADC_i, RST_8H,
  RET_NC, POP_DE,   JP_NC, OUT_A,    CALL_NC, PUSH_DE, SUB_i, RST_10H,
  RET_C,  EXX,      JP_C,  IN_A,     CALL_C,  PFX_DD,  SBC_i, RST_18H,
  RET_PO, POP_HL,   JP_PO, EX_HL_SP, CALL_PO, PUSH_HL, AND_i, RST_20H,
  RET_PE, LD_PC_HL, JP_PE, EX_DE_HL, CALL_PE, PFX_ED,  XOR_i, RST_28H,
  RET_P,  POP_AF,   JP_P,  DI,       CALL_P,  PUSH_AF, OR_i,  RST_30H,
  RET_M,  LD_SP_HL, JP_M,  EI,       CALL_M,  PFX_FD,  CP_i,  RST_38H
};

static const byte EEcycles[256] =
{
    4, 10, 7,  5,  5,  5,  7,  4,  0, 10, 7,  5,  5,  5,  7, 4,
    0, 10, 7,  5,  5,  5,  7,  4,  0, 10, 7,  5,  5,  5,  7, 4,
    0, 10, 16, 5,  5,  5,  7,  4,  0, 10, 16, 5,  5,  5,  7, 4,
    0, 10, 13, 5,  10, 10, 10, 4,  0, 10, 13, 5,  5,  5,  7, 4,
    5, 5,  5,  5,  5,  5,  7,  5,  5, 5,  5,  5,  5,  5,  7, 5,
    5, 5,  5,  5,  5,  5,  7,  5,  5, 5,  5,  5,  5,  5,  7, 5,
    5, 5,  5,  5,  5,  5,  7,  5,  5, 5,  5,  5,  5,  5,  7, 5,
    7, 7,  7,  7,  7,  7,  7,  7,  5, 5,  5,  5,  5,  5,  7, 5,
    4, 4,  4,  4,  4,  4,  7,  4,  4, 4,  4,  4,  4,  4,  7, 4,
    4, 4,  4,  4,  4,  4,  7,  4,  4, 4,  4,  4,  4,  4,  7, 4,
    4, 4,  4,  4,  4,  4,  7,  4,  4, 4,  4,  4,  4,  4,  7, 4,
    4, 4,  4,  4,  4,  4,  7,  4,  4, 4,  4,  4,  4,  4 , 7, 4,
    5, 10, 10, 10, 11, 11, 7,  11, 5, 10, 10, 0,  11, 17, 7, 11,
    5, 10, 10, 10, 11, 11, 7,  11, 5, 0,  10, 10, 11, 0,  7, 11,
    5, 10, 10, 18, 11, 11, 7,  11, 5, 5,  10, 4,  11, 0,  7, 11,
    5, 10, 10, 4,  11, 11, 7,  11, 5, 5,  10, 4,  11, 0,  7, 11
};

#ifdef DEBUG
static const char EEmnmonic[][256] =
{
  "NOP","LD BC,#h","LD (BC),A","INC BC","INC B","DEC B","LD B,*h","RLCA",
  "EX AF,AF'","ADD HL,BC","LD A,(BC)","DEC BC","INC C","DEC C","LD C,*h","RRCA",
  "DJNZ @h","LD DE,#h","LD (DE),A","INC DE","INC D","DEC D","LD D,*h","RLA",
  "JR @h","ADD HL,DE","LD A,(DE)","DEC DE","INC E","DEC E","LD E,*h","RRA",
  "JR NZ,@h","LD HL,#h","LD (#h),HL","INC HL","INC H","DEC H","LD H,*h","DAA",
  "JR Z,@h","ADD HL,HL","LD HL,(#h)","DEC HL","INC L","DEC L","LD L,*h","CPL",
  "JR NC,@h","LD SP,#h","LD (#h),A","INC SP","INC (HL)","DEC (HL)","LD (HL),*h","SCF",
  "JR C,@h","ADD HL,SP","LD A,(#h)","DEC SP","INC A","DEC A","LD A,*h","CCF",
  "LD B,B","LD B,C","LD B,D","LD B,E","LD B,H","LD B,L","LD B,(HL)","LD B,A",
  "LD C,B","LD C,C","LD C,D","LD C,E","LD C,H","LD C,L","LD C,(HL)","LD C,A",
  "LD D,B","LD D,C","LD D,D","LD D,E","LD D,H","LD D,L","LD D,(HL)","LD D,A",
  "LD E,B","LD E,C","LD E,D","LD E,E","LD E,H","LD E,L","LD E,(HL)","LD E,A",
  "LD H,B","LD H,C","LD H,D","LD H,E","LD H,H","LD H,L","LD H,(HL)","LD H,A",
  "LD L,B","LD L,C","LD L,D","LD L,E","LD L,H","LD L,L","LD L,(HL)","LD L,A",
  "LD (HL),B","LD (HL),C","LD (HL),D","LD (HL),E","LD (HL),H","LD (HL),L","HALT","LD (HL),A",
  "LD A,B","LD A,C","LD A,D","LD A,E","LD A,H","LD A,L","LD A,(HL)","LD A,A",
  "ADD B","ADD C","ADD D","ADD E","ADD H","ADD L","ADD (HL)","ADD A",
  "ADC B","ADC C","ADC D","ADC E","ADC H","ADC L","ADC (HL)","ADC A",
  "SUB B","SUB C","SUB D","SUB E","SUB H","SUB L","SUB (HL)","SUB A",
  "SBC B","SBC C","SBC D","SBC E","SBC H","SBC L","SBC (HL)","SBC A",
  "AND B","AND C","AND D","AND E","AND H","AND L","AND (HL)","AND A",
  "XOR B","XOR C","XOR D","XOR E","XOR H","XOR L","XOR (HL)","XOR A",
  "OR B","OR C","OR D","OR E","OR H","OR L","OR (HL)","OR A",
  "CP B","CP C","CP D","CP E","CP H","CP L","CP (HL)","CP A",
  "RET NZ","POP BC","JP NZ,#h","JP #h","CALL NZ,#h","PUSH BC","ADD *h","RST 00h",
  "RET Z","RET","JP Z,#h","PFX_CB","CALL Z,#h","CALL #h","ADC *h","RST 08h",
  "RET NC","POP DE","JP NC,#h","OUTA (*h)","CALL NC,#h","PUSH DE","SUB *h","RST 10h",
  "RET C","EXX","JP C,#h","INA (*h)","CALL C,#h","PFX_DD","SBC *h","RST 18h",
  "RET PO","POP HL","JP PO,#h","EX HL,(SP)","CALL PO,#h","PUSH HL","AND *h","RST 20h",
  "RET PE","LD PC,HL","JP PE,#h","EX DE,HL","CALL PE,#h","PFX_ED","XOR *h","RST 28h",
  "RET P","POP AF","JP P,#h","DI","CALL P,#h","PUSH AF","OR *h","RST 30h",
  "RET M","LD SP,HL","JP M,#h","EI","CALL M,#h","PFX_FD","CP *h","RST 38h"
};
#endif

#endif
